The present invention relates to a semiconductor integrated circuit device making use of an area pad and a wiring arranging method thereof.
A signal between a chip of a semiconductor integrated circuit and a package is inputted/outputted through a wiring arranged in an I/O slot of the chip and a wiring between input/output pads. An I/O cell, e.g., input/output buffer, is connected to the I/O slot. Each of the I/O slot and the wiring arranged in the I/O slot is called I/O slot herein later.
As shown in FIG. 3, an I/O slot 11 is arranged in a periphery of a chip 40, and a plurality of pads are arranged in a lattice form over the entire region of the chip 40. The pad arranged over the entire region of the chip 40, not only in a periphery of the chip 40, is called an area pad 12.
The area pad 12 is also arranged in a central portion of the chip 40. Therefore, the number of pads per chip 40 can be increased without unduly diminishing a pad pitch 41, compared with the case where the pads are arranged in only the periphery of the chip 40.
In an ASIC (Application Specific Integrated Circuit), the I/O slot and the area pad arranged in the outer periphery of the chip are used as wirings that are generally formed on the uppermost layer. In the wiring pattern formed on the uppermost layer of the chip, redesign for each chip is not performed, and used is a standard pattern in which the connecting relationship between the wiring and the pad is designed in advance.
It is impossible to diminish the pad 12 in the design step. Further, the width of the I/O slot 11 is sufficiently small, compared with the pad 12. As a result, if the pads 12 are arranged in the adjacent I/O slots 11, these pads 12 are positioned contiguous to each other. To overcome this difficulty, the pad pitch 41 is set at a sufficiently large value as shown in FIG. 3.
The connection between the I/O slot and the area pad within the chip will now be described with reference to FIG. 4. The upper region of the drawing represents the chip inner area, with the lower region representing the outermost peripheral area of the chip.
As shown in FIG. 4, I/O slots 11a, 11b, 11c, 11d are arranged within the chip inner area. Pads 12a, 12b are arranged above the I/O slot 11a among these I/O slots 11a to 11d. The pad 12a is connected to the I/O slot 11a via a wiring 14 and a via 15. Likewise, the pad 12b is connected to the I/O slot 11b via a wiring 17 and a via 18. These wirings 14, 17 constitute the standard pattern of the uppermost layer of the chip inner area.
Defect analyzing pads 13a, 13b are arranged in the chip outermost peripheral area. The wiring 14 is connected to the defect analyzing pad 13a through the via 15 and a wiring 16. Also, the wiring 17 is connected to the defect analyzing pad 13b through the via 18 and a wiring 19.
It should be noted that the pad 12a is positioned close to the peripheral portion of the chip; whereas, the pad 12b is positioned remote from the peripheral portion of the chip. As a result, the wiring 17 between the pad 12b and the via 18 is rendered long, though the wiring 14 between the pad 12a and the via 15 is short, as shown in FIG. 4.
As described above, the short wiring 14 and the long wiring 17 are formed in the standard pattern in the uppermost layer of the chip inner area. If the wiring is long like the wiring 17, problems such as delay of the signal transmission are generated. To be more specific, where an I/O cell requiring a high speed performance is alloted to the I/O slot 11b to which is connected the long wiring 17, a delay of signal transmission takes place. It follows that it is necessary to change the position of the I/O slot requiring a high speed performance to the position of the I/O slot 11a to which is connected the short wiring 14. However, the chip must be redesigned for changing the position of the I/O slot, leading to a high manufacturing cost.